One of the most common requests we get is to offer a 5-day training instead. Each day of the training includes one assignment focusing on one common issue related to hardware security and takes approximately one day to solve. The fifth day of the training now includes …

Real test and measurement equipment and Xilinx 7-series FPGAs.

Normally for our trainings we use Saleae Logic Analyzers. But in Berlin, we’re able to offer students a unique opportunity to work with real test and measurement equipment. Students who attend the training will get a chance to work with modern digital storage oscilloscopes, so don’t miss out.  Last year, we switched to the Xilinx Artix 7 series FPGAs. We’re also now utilizing the latest and greatest Xilinx Vivado design suite for our projects. Of course, all of these changes have made it into our training courses as well. We’ll teach you how to work with these advanced tools by putting it all to good use at one of our trainings. As always, registration includes our favorite FPGA development board, the Digilent Arty, to keep.

No Hardware Background? No Problem.

The course is ideally suited for both hardware engineers who wish to better understand potential security issues that may exist in hardware implementations and software security engineers who may lack experience in analyzing hardware and embedded systems. In general the course will teach a hybrid hardware/software workflow that is extremely effective for identifying security issues in hardware. The workflow consists of implementing complex algorithms in a modern high-level scripting language (python) and implementing all low-level timing critical components in hardware (verilog HDL). This training will also cover how these techniques can be utilized for applications ranging from black box reverse-engineering of undocumented protocols to validating an overall hardware design.

As such there are no specific prerequisites for this course beyond a basic programming background. Students will be provided sufficient background and templates for the python scripting language to successfully complete the assignments. All the aspects of hardware design (RTL design, verilog HDL as well as simulation and verification) will be covered in the course. Each day will feature one CTF (capture the flag) style assignment that will take approximately the entire day for students to solve. Each assignment will cover one common flaw that can be found in real-world hardware implementations.

Students who complete this course should be able to perform any of the following tasks:

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